RISC-V

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  1. Many RISC-V computers might implement the compact extension to reduce power consumption, code size, and memory use.[1]
  2. These can simulate most of the other RISC-V instruction sets with software.[1]
  3. RISC-V computers without floating-point can use a floating-point software library.[1]
  4. The preliminary FreeBSD port to the RISC-V architecture was upstreamed in February 2016, and shipped in FreeBSD 11.0.[1]
  5. In October, I asked Arm CEO Simon Segars about RISC-V in an interview during Arm’s conference in the same convention center.[2]
  6. Ted Speers, head of architecture and planning at Microchip, said he first heard about RISC-V during a meeting in December 2014.[2]
  7. It was a risk to use RISC-V, but the company expects to introduce RISC-V across a large number of products in the future, including AI, security, and safety chips, Huh said.[2]
  8. The RISC-V ISA we invented is configurable and extensible, and our processor cores are, too.[3]
  9. We first noticed Micro Magic's claims earlier this week, when EE Times reported on the company's new prototype CPU, which appears to be the fastest RISC-V CPU in the world.[4]
  10. Micro Magic intends to offer its new RISC-V design to customers using an IP licensing model.[4]
  11. Development tools, software libraries, and operating system ports (including Linux) are all part of the current RISC-V support ecosystem.[5]
  12. Two key documents define the RISC-V ISA: The User-Level ISA Specification and the Privileged ISA Specification.[5]
  13. Somewhere along the line the team decided it would be interesting and challenging to design the fastest, most power-efficient RISC-V implementation they could manage.[6]
  14. At top speed, the chip scores 13,000 on the CoreMark benchmark, which makes it the fastest RISC-V processor in existence, according to Huang.[6]
  15. “Several years ago, what the ecosystem was trying to do was basically make RISC-V IP available,” he said.[7]
  16. For system architects getting into RISC-V for the first time, Silicon Labs’ Richmond recommends taking advantage of the infrastructure and the ecosystem that is already in place.[7]
  17. Cobham Gaisler’s NOEL-V, on the other hand, is a synthesizable VHDL model of a processor that implements the RISC-V architecture.[8]
  18. The Green Hills compiler supports the modular nature of the RISC-V architecture by allowing the user to choose exactly the instruction set modules they would like to compiler their code for.[9]
  19. A popular feature of the open RISC-V architecture is that users can incorporate their own custom instructions into their design.[9]
  20. RISC-V ISA (Instruction Set Architecture) is designed in a modular way.[10]
  21. It can be compiled with any compiler compatible with a standard RISC-V processor (no special ISA extensions).[10]
  22. Figure 2 below shows another example of a RISC-V-compliant processor with a custom ISA extension.[10]
  23. When it comes to ISA extensions, designers usually start with a full-blown RISC-V-compliant processor written in CodAL, delivered by Codasip.[10]
  24. The Lattice Semiconductor RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).[11]
  25. DAC invites all RISC-V company members to exhibit at the 58th DAC in San Francisco.[12]
  26. Several RISC-V development efforts are targeting applications such as artificial intelligence (AI), machine learning (ML), deep learning (DL), and other high-performance embedded applications.[13]
  27. The initial RISC-V product from Cobham Gaisler will be an RV64GC compliant processor IP core, a 64-bit architecture, written in VHDL.[13]
  28. GRLIB offers several interfaces and functions such as high-speed serial interconnect, encryption, compression, and so on, which can be embedded with the RISC-V processor.[13]
  29. Esperanto’s high-performance ET-Maxion core is designed to deliver the best single-thread RISC-V performance.[13]
  30. Sure, a RISC-V IP design must be compliant to basic ISA standards and should contain a testing suite demonstrating that compliance.[14]
  31. The following rule sets - which are four of many sets at the heart of ALINT-PRO and accessed through a structured library of chapters and sections - are now available with a RISC-V focus.[14]
  32. The fourth set of rules to be given an RISC-V focus, SystemVerilog Constructs, ensures optimal SystemVerilog usage for the RTL coding.[14]
  33. Micro Magic has introduced what it claims is the world’s fastest 64-bit RISC-V core — a device it says outperforms the Apple M1 chip and Arm Cortex-A9.[15]

소스

  1. ↑ 1.0 1.1 1.2 1.3 Wikipedia
  2. ↑ 2.0 2.1 2.2 RISC-V grows globally as an alternative to Arm and its license fees
  3. ↑ SiFive
  4. ↑ 4.0 4.1 New RISC-V CPU claims recordbreaking performance per watt
  5. ↑ 5.0 5.1 Creating a Custom Processor with RISC-V
  6. ↑ 6.0 6.1 Tiny Firm Makes Super-Fast RISC-V
  7. ↑ 7.0 7.1 RISC-V Verification Challenges Spread
  8. ↑ Cobham Gaisler and fentISS Deepen Collaboration around RISC-V
  9. ↑ 9.0 9.1 RISC-V Embedded Software Solutions for Green Hills Software
  10. ↑ 10.0 10.1 10.2 10.3 Extending RISC-V ISA With a Custom Instruction Set Extension
  11. ↑ RISC-V MC CPU IP Core
  12. ↑ Design Automation Conference
  13. ↑ 13.0 13.1 13.2 13.3 RISC-V for artificial intelligence machine learning and embedded systems
  14. ↑ 14.0 14.1 14.2 Linting RISC-V designs with ALINT-PRO
  15. ↑ Micro Magic RISC-V Core Claims to Beat Apple M1 and Arm Cortex-A9

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